The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2006

Filed:

Jun. 30, 2003
Applicants:

Gary A. Brist, Yamhill, OR (US);

Gary B. Long, Aloha, OR (US);

William O. Alger, Portland, OR (US);

Dennis J. Miller, Sherwood, OR (US);

Inventors:

Gary A. Brist, Yamhill, OR (US);

Gary B. Long, Aloha, OR (US);

William O. Alger, Portland, OR (US);

Dennis J. Miller, Sherwood, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/16 (2006.01);
U.S. Cl.
CPC ...
Abstract

An I/O routing pattern method is disclosed, for use with heterogeneous printed circuit boards (PCBs), such as those embedded with a reinforcement material, for example, a fiberglass weave. Traces are routed on the PCB so as to reduce sensitivity to changes in the dielectric constant (D), which are brought about by the strands of reinforcement material contained within the PCB laminate. The method minimizes the local variations, such as the D, time of flight, and capacitance variations, that are observed with traditional routing methods on heterogeneous PCBs.


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