The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 28, 2006
Filed:
Apr. 28, 2004
John M. Dicosola, Pleasanton, CA (US);
Adam Wright, San Jose, CA (US);
Junzhao J. Lei, Santa Clara, CA (US);
Mark A. Banke, San Jose, CA (US);
William Hata, Saratoga, CA (US);
John M. Dicosola, Pleasanton, CA (US);
Adam Wright, San Jose, CA (US);
Junzhao J. Lei, Santa Clara, CA (US);
Mark A. Banke, San Jose, CA (US);
William Hata, Saratoga, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Systems and methods are provided for marking integrated circuit defects on wafers to facilitate failure analysis. A wafer containing integrated circuits can be tested using a tester. Test data from the tester can be analyzed using integrated circuit design files to identify suspected faults. A fault location program can be used to identify the physical location of the faults. The fault location program uses information on the faults identified and CAD file information on the physical layout of the integrated circuit to map identified faults to actual physical positions. The fault location program may also generate laser control files. The laser control files can be used to control a laser system so that the laser system creates laser marks on the wafer surrounding each of the faults. The marked faults can be polished and examined under an electron microscope or analyzed using other failure analysis tools.