The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 28, 2006
Filed:
Dec. 09, 2003
Jochen C. Beintner, Wappingers Falls, NY (US);
Dureseti Chidambarrao, Weston, CT (US);
Yujun LI, Poughkeepsie, NY (US);
Kenneth T. Settlemyer, Jr., Poughquag, NY (US);
Jochen C. Beintner, Wappingers Falls, NY (US);
Dureseti Chidambarrao, Weston, CT (US);
Yujun Li, Poughkeepsie, NY (US);
Kenneth T. Settlemyer, Jr., Poughquag, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of forming integrated circuits having FinFET transistors includes a method of forming sub-lithographic fins, in which a mask defining a block of silicon including a pair of fins in reduced in width or pulled back by the thickness of one fin on each side, after which a second mask is formed around the first mask, so that after the first mask is removed, an aperture remains in the second mask having the width of the separation distance between the pair of fins. When the silicon is etched through the aperture, the fins are protected by the second mask, thereby defining fin thickness by the pullback step. An alternative method uses lithography of opposite polarity, first defining the central etch aperture between the two fins lithographically, then expanding the width of the aperture by a pullback step, so that filling the widened aperture with an etch-resistant plug defines the outer edges of the pair of fins, thereby setting the fin width without an alignment kstep.