The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 2006
Filed:
May. 14, 2004
Jeffrey S. Brown, Middlesex, VT (US);
Chung H. Lam, Williston, VT (US);
Randy W. Mann, Poughquag, NY (US);
Jeffery H. Oppold, Richmond, VT (US);
Jeffrey S. Brown, Middlesex, VT (US);
Chung H. Lam, Williston, VT (US);
Randy W. Mann, Poughquag, NY (US);
Jeffery H. Oppold, Richmond, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A zero threshold voltage (ZVt) pFET () and a method of making the same. The ZVt pFET is made by implanting a p-type substrate () with a retrograde n-well () so that a pocket () of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask () having a pocket-masking region () in the aperture () corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well () and then annealing the substrate so as to cause the regions of the lower portion () of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (), gate (), source (), and drain ().