The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2006
Filed:
Feb. 10, 2003
Minh Quoc Tran, Milpitas, CA (US);
LU You, San Jose, CA (US);
Fei Wang, San Jose, CA (US);
Lynne Okada, Sunnyvale, CA (US);
Minh Quoc Tran, Milpitas, CA (US);
Lu You, San Jose, CA (US);
Fei Wang, San Jose, CA (US);
Lynne Okada, Sunnyvale, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
An interconnect structure is formed with a plurality of layers of a conductive material with a grain boundary between any two adjacent layers of the conductive material. Such grain boundaries between layers of conductive material act as shunt by-pass paths for migration of atoms of the conductive material to minimize migration of atoms of the conductive material along the interface between a dielectric passivation or capping layer and the interconnect structure. When the interconnect structure is a via structure, each of the layers of the conductive material and each of the grain boundary are formed to be perpendicular to a direction of current flow through the via structure. Such grain boundaries formed between the plurality of layers of conductive material in the via structure minimize charge carrier wind-force along the direction of current flow through the via structure to further minimize electromigration failure of the via structure.