The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6994243 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 07, 2006

Filed:

Oct. 26, 2004
Applicants:

Joseph M. Milewski, Kirkwood, NY (US);

Charles G. Woychik, Vestal, NY (US);

Inventors:

Joseph M. Milewski, Kirkwood, NY (US);

Charles G. Woychik, Vestal, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
B23K 31/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A solder interconnection uses preferably lead-rich solder balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate. After a solder ball has been formed using standard processes, a thin cap layer of preferably pure tin is deposited on a surface of the solder balls. An interconnecting eutectic alloy is formed upon reflow. Subsequent annealing causes tin to diffuse into the lead, or vice versa, and intermix, thereby raising the melting point temperature of the cap layer of the resulting assembly. This structure and process avoids secondary reflow problems during subsequent processing.


Find Patent Forward Citations

Milewski, Joseph. (2006). Low temperature solder chip attach structure and process to produce a high temperature interconnection (U.S. Patent No. 6994243). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6994243

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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