The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 31, 2006
Filed:
Jan. 10, 2005
Bruno Ghyselen, Seyssinet-Pariset, FR;
Cécile Aulnette, Grenoble, FR;
Bénédite Osternaud, Saint Egreve, FR;
Nicolas Daval, Grenoble, FR;
Bruno Ghyselen, Seyssinet-Pariset, FR;
Cécile Aulnette, Grenoble, FR;
Bénédite Osternaud, Saint Egreve, FR;
Nicolas Daval, Grenoble, FR;
S.O.I.Tec Silicon on Insulator Technologies S.A., Bernin, FR;
Abstract
A method for transferring a layer of semiconductor material from a wafer is described. The wafer includes a support substrate and an upper surface that includes a buffer layer of a material having a first lattice parameter. In an embodiment, the technique includes growing a strained layer on the buffer layer. The strained layer is made of a semiconductor material having a nominal lattice parameter that is substantially different from the first lattice parameter, and it is grown to a thickness that is sufficiently thin to avoid relaxation of the strain therein. The method also includes growing a relaxed layer on the strained layer. The relaxed layer is made of silicon and has a concentration of at least one other semiconductor material that has a nominal lattice parameter that is substantially identical to the first lattice parameter. The technique also includes providing a weakened zone in the buffer layer, and supplying energy to detach a structure at the weakened zone. The structure includes a portion of the buffer layer, the strained layer and the relaxed layer. Lastly; the method includes enriching the concentration of the at least one other semiconductor material in the relaxed layer of the structure.