The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 24, 2006
Filed:
Mar. 30, 2001
Masaharu Kubo, Hachioji, JP;
Ichiro Anjo, Koganei, JP;
Akira Nagai, Hitachi, JP;
Osamu Kubo, Hitachi, JP;
Hiromi Abe, Hitachinaka, JP;
Hitoshi Akamine, Maebashi, JP;
Masaharu Kubo, Hachioji, JP;
Ichiro Anjo, Koganei, JP;
Akira Nagai, Hitachi, JP;
Osamu Kubo, Hitachi, JP;
Hiromi Abe, Hitachinaka, JP;
Hitoshi Akamine, Maebashi, JP;
Renesas Technology Corporation, Tokyo, JP;
Abstract
CMOS logic LSI comprises, as a part thereof, n-channel MISFET's (Qn), p-channel MISFET's (Qp) and a first-layer wiring () to a third-layer () formed on a main surface of a silicon substrate (), and as another part, a fourth-layer wiring () to a seventh-layer wiring () formed on a main surface of a glass substrate () different from the silicon substrate (). The main surface of the silicon substrate () and the main surface of the glass substrate () are arranged in face-to-face relation with each other, and a plurality of microbumps (A) formed at the uppermost portion of the silicon substrate () and a plurality of microbumps (B) formed at the uppermost portion of the glass substrate () are electrically connected, thereby constituting the CMOS logic LSI as a whole.