The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 24, 2006
Filed:
Dec. 09, 2003
Mamoru Ito, Tamamura, JP;
Akira Muto, Haruna, JP;
Tomio Yamada, Tamamura, JP;
Tsuneo Endoh, Komoro, JP;
Satoru Konishi, Saku, JP;
Kazuaki Uehara, Saku, JP;
Tsutomu Ida, Komoro, JP;
Koji Odaira, Takasaki, JP;
Hirokazu Nakajima, Saku, JP;
Mamoru Ito, Tamamura, JP;
Akira Muto, Haruna, JP;
Tomio Yamada, Tamamura, JP;
Tsuneo Endoh, Komoro, JP;
Satoru Konishi, Saku, JP;
Kazuaki Uehara, Saku, JP;
Tsutomu Ida, Komoro, JP;
Koji Odaira, Takasaki, JP;
Hirokazu Nakajima, Saku, JP;
Renesas Technology Corp., Tokyo, JP;
Renesas Esatern Japan Semiconductor, Inc., Tokyo, JP;
Abstract
There is provided a semiconductor device with enhanced reliability having a heat sink mounting a plurality of semiconductor chips, a plurality of inner leads connected electrically to the semiconductor chips, a molding body for resin molding the plurality of semiconductor chips and the plurality of inner leads, a plurality of wires for providing electrical connections between the respective electrodes of the semiconductor chips and the inner leads corresponding thereto, and wide outer leads connecting to the inner leads and exposed outside the molding body. A plurality of slits are formed in the respective portions of the outer leads located outside the molding body to extend lengthwise in directions in which the outer leads are extracted. This achieves a reduction in lead stress which is placed on the outer leads by thermal stress or the like after the mounting of a MOSFET and thereby enhances the reliability of the MOSFET.