The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 17, 2006
Filed:
Dec. 20, 2002
Christophe Pierrat, Santa Clara, CA (US);
You-ping Zhang, Newark, CA (US);
Fang-cheng Chang, Sunnyvale, CA (US);
Hoyong Park, Sunnyvale, CA (US);
Yao-ting Wang, Atherton, CA (US);
Christophe Pierrat, Santa Clara, CA (US);
You-Ping Zhang, Newark, CA (US);
Fang-Cheng Chang, Sunnyvale, CA (US);
Hoyong Park, Sunnyvale, CA (US);
Yao-Ting Wang, Atherton, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
A semiconductor layout testing and correction system is disclosed. The system combines both rule-based optical proximity correction and model-based optical proximity correction in order to test and correct semiconductor layouts. In a first embodiment, a semiconductor layout is first processed by a rule-based optical proximity correction system and then subsequently processed by a model-based optical proximity correction system. In another embodiment, the system first processes a semiconductor layout with a rule-based optical proximity correction system and then selectively processes difficult features using a model-based optical proximity correction system. In yet another embodiment, the system selectively processes the various features of a semiconductor layout using a rule-based optical proximity correction system or a model-based optical proximity correction system.