The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 17, 2006
Filed:
Oct. 24, 2002
Hiroshi Kujirai, Kunitachi, JP;
Masahiro Moniwa, Sayama, JP;
Kazuo Nakazato, Cambridge, GB;
Teruo Kisu, Legal Representative, Tokyo, JP;
Haruko Kisu, Legal Representative, Tokyo, JP;
Hideyuki Matsuoka, Nishi-tokyo, JP;
Tsuyoshi Tabata, Futaba, JP;
Satoru Haga, Akishima, JP;
Hiroshi Kujirai, Kunitachi, JP;
Masahiro Moniwa, Sayama, JP;
Kazuo Nakazato, Cambridge, GB;
Teruo Kisu, legal representative, Tokyo, JP;
Haruko Kisu, legal representative, Tokyo, JP;
Hideyuki Matsuoka, Nishi-tokyo, JP;
Tsuyoshi Tabata, Futaba, JP;
Satoru Haga, Akishima, JP;
Hitachi, Ltd., Tokyo, JP;
Hitachi ULSI Systems Co., LTD, Tokyo, JP;
Abstract
A vertical MIS is provided immediately above a trench-type capacitor provided in a memory cell forming region of a semiconductor substrate, and a lateral nMIS is provided in the peripheral circuit forming region of the semiconductor substrate. After forming the capacitor, the lateral nMIS is formed. In addition, after forming the lateral nMIS, the vertical MIS is formed. Furthermore, after forming a capacitor, an isolation part of the peripheral circuit is formed.