The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2006

Filed:

May. 02, 2002
Applicants:

Keng L. Wong, Portland, OR (US);

Niraj Bindal, Hillsboro, OR (US);

Hong-piao MA, Portland, OR (US);

George Geannopoulos, Portland, OR (US);

Greg F. Taylor, Portland, OR (US);

Edward A. Burton, Hillsboro, OR (US);

Inventors:

Keng L. Wong, Portland, OR (US);

Niraj Bindal, Hillsboro, OR (US);

Hong-Piao Ma, Portland, OR (US);

George Geannopoulos, Portland, OR (US);

Greg F. Taylor, Portland, OR (US);

Edward A. Burton, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03B 27/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A clock generating circuit is provided that includes a multiplexing device coupled to a clock distribution network to select between a synchronous mode and an asynchronous mode. The device may also include a plurality of distributed ring oscillators to drive the clock distribution network in the asynchronous mode. In the synchronous mode, the multiplexing device may pass a signal from a phase lock loop circuit located external to a core.


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