The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 20, 2005
Filed:
Jun. 04, 2003
L. Elliott Pflughaupt, Los Gatos, CA (US);
David Gibson, Lake Oswego, OR (US);
Young-gon Kim, Cupertino, CA (US);
Craig S. Mitchell, San Jose, CA (US);
Wael Zohni, Newark, CA (US);
Ilyas Mohammed, Santa Clara, CA (US);
L. Elliott Pflughaupt, Los Gatos, CA (US);
David Gibson, Lake Oswego, OR (US);
Young-Gon Kim, Cupertino, CA (US);
Craig S. Mitchell, San Jose, CA (US);
Wael Zohni, Newark, CA (US);
Ilyas Mohammed, Santa Clara, CA (US);
Tessera, Inc., San Jose, CA (US);
Abstract
A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively connected, as by forming solder bridges, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses. The individual units desirably are thin and directly abut one another so as to provide a low-height assembly with good heat transfer from chips within the stack.