The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 29, 2005
Filed:
Nov. 03, 2003
Robert J. Chiu, Santa Clara, CA (US);
Paul R. Besser, Sunnyvale, CA (US);
Simon Siu-sing Chan, Saratoga, CA (US);
Jeffrey P. Patton, Santa Clara, CA (US);
Austin C. Frenkel, San Jose, CA (US);
Thorsten Kammler, Ottendorft-Okrilla, DE;
Errol Todd Ryan, Wappingers Fall, NY (US);
Robert J. Chiu, Santa Clara, CA (US);
Paul R. Besser, Sunnyvale, CA (US);
Simon Siu-Sing Chan, Saratoga, CA (US);
Jeffrey P. Patton, Santa Clara, CA (US);
Austin C. Frenkel, San Jose, CA (US);
Thorsten Kammler, Ottendorft-Okrilla, DE;
Errol Todd Ryan, Wappingers Fall, NY (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A method of forming an integrated circuit, and an integrated circuit, are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.