The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2005

Filed:

Feb. 07, 2002
Applicants:

Ian Bryant, Sunnyvale, CA (US);

Chung-yuan Sun, San Jose, CA (US);

Sheng Feng, Cupertino, CA (US);

Jung-cheun Lien, San Jose, CA (US);

Stephen Chan, San Jose, CA (US);

Inventors:

Ian Bryant, Sunnyvale, CA (US);

Chung-Yuan Sun, San Jose, CA (US);

Sheng Feng, Cupertino, CA (US);

Jung-Cheun Lien, San Jose, CA (US);

Stephen Chan, San Jose, CA (US);

Assignee:

Actel Corporation, Mountain View, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R031/28 ; G06G007/48 ; H03K017/693 ;
U.S. Cl.
CPC ...
Abstract

A method of accessing the testing means in a Field Programmable Gate Array ('FPGA') comprised of a plurality of functional groups ('FGs') comprising: inputting a function netlist defining a user circuit; compiling said function netlist; and generating a logic Built-In Self Test (“BIST”) netlist; wherein said BIST netlist replaces all user registers with scan registers with a scan chain routed as the physical silicon scan chains.


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