The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2005
Filed:
Sep. 13, 2000
Applicants:
Dieter Rathei, F-75011 Paris, FR;
Peter Oswald, Richmond, VA (US);
Thomas Hladschik, Glen Allen, VA (US);
Joerg Wohlfahrt, Glen Allen, VA (US);
Inventors:
Dieter Rathei, F-75011 Paris, FR;
Peter Oswald, Richmond, VA (US);
Thomas Hladschik, Glen Allen, VA (US);
Joerg Wohlfahrt, Glen Allen, VA (US);
Assignee:
Other;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01N037/00 ; G06F019/00 ;
U.S. Cl.
CPC ...
Abstract
A method for classifying patterns of failcodes on a semiconductor wafer, in accordance with the present invention, includes determining failcodes for chips on the wafer and checking adjacent chips for each chip on the wafer having a failcode to determine a failcode pattern having a defined number of chips.
Rathei, Dieter. (2005). Method and apparatus for fast automated failure classification for semiconductor wafers (U.S. Patent No. 6963813). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6963813
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile