The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2005
Filed:
Oct. 21, 2004
Hiroshi Funakura, Kanagawa-ken, JP;
Eiichi Hosomi, Kanagawa-ken, JP;
Yasuhiro Koshio, Kanagawa-ken, JP;
Tetsuya Nagaoka, Kanagawa-ken, JP;
Junya Nagano, Kanagawa-ken, JP;
Mitsuru Oida, Kanagawa-ken, JP;
Masatoshi Fukuda, Kanagawa-ken, JP;
Atsushi Kurosu, Tokyo, JP;
Kaoru Kawai, Kanagawa-ken, JP;
Osamu Yamagata, Kanagawa-ken, JP;
Hiroshi Funakura, Kanagawa-ken, JP;
Eiichi Hosomi, Kanagawa-ken, JP;
Yasuhiro Koshio, Kanagawa-ken, JP;
Tetsuya Nagaoka, Kanagawa-ken, JP;
Junya Nagano, Kanagawa-ken, JP;
Mitsuru Oida, Kanagawa-ken, JP;
Masatoshi Fukuda, Kanagawa-ken, JP;
Atsushi Kurosu, Tokyo, JP;
Kaoru Kawai, Kanagawa-ken, JP;
Osamu Yamagata, Kanagawa-ken, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.