The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 25, 2005
Filed:
Oct. 17, 2003
Evgeni P. Gousev, Mahopac, NY (US);
Harald F. Okorn-schmidt, Putnam Valley, NY (US);
Arne W. Ballantine, Round Lake, NY (US);
Douglas A. Buchanan, Cortlandt Manor, NY (US);
Eduard A. Cartier, Leuven, BE;
Douglas D. Coolbaugh, Essex Junction, VT (US);
Evgeni P. Gousev, Mahopac, NY (US);
Harald F. Okorn-Schmidt, Putnam Valley, NY (US);
Arne W. Ballantine, Round Lake, NY (US);
Douglas A. Buchanan, Cortlandt Manor, NY (US);
Eduard A. Cartier, Leuven, BE;
Douglas D. Coolbaugh, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Methods of forming front-end-of the line (FEOL) capacitors such as polysilicon-polysilicon capacitors and metal-insulator-silicon capacitors are provided that are capable of incorporating a high-dielectric constant (k of greater than about 8) into the capacitor structure. The inventive methods provide high capacitance/area devices with low series resistance of the top and bottom electrodes for high frequency responses. The inventive methods provide a significant reduction in chip size, especially in analog and mixed-signal applications where large areas of capacitance are used.