High density chip level package for the packaging of integrated circuits and method to manufacture same

Abstract

A package for mounting an integrated circuit die. In one embodiment the package comprises a metal substrate having first and second opposing primary surfaces and an aperture formed therebetween. A flexible thin film interconnect structure is formed over the first surface of the metal substrate and over the aperture. The flexible thin film interconnect structure has bottom and top opposing surfaces, a first region that is in direct contact with the first surface of the metal substrate and a second region that is opposite the aperture. The bottom surface of the thin film interconnect structure is in direct contact with the metal substrate in the first region. The thin film interconnect structure comprises (i) a first dielectric layer formed directly on the first surface of the metal substrate and extending over the aperture; (ii) a first metalization layer, formed over the first dielectric layer, comprising a plurality of signal lines positioned over the first region of the thin film interconnect structure and a first plurality of bonding pads positioned over the second region of the thin film interconnect structure; and (iii) a second plurality of bonding pads on the top surface of the thin film interconnect structure. The first plurality of bonding pads have a first pitch appropriate for attaching the integrated circuit die to the package and the second plurality of bonding pads have a pitch greater than the first pitch. Other embodiments of chip level packages as well as various methods for forming such packages are also disclosed.