The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 11, 2005
Filed:
Jun. 12, 2002
Jong-kai Lin, Chandler, AZ (US);
William H. Lytle, Chandler, AZ (US);
Owen Fay, Gilbert, AZ (US);
Steven Markgraf, Chandler, AZ (US);
Henry G. Hughes, Scottsdale, AZ (US);
Craig Amrine, Tempe, AZ (US);
Ananda P. DE Silva, Chandler, AZ (US);
Jong-Kai Lin, Chandler, AZ (US);
William H. Lytle, Chandler, AZ (US);
Owen Fay, Gilbert, AZ (US);
Steven Markgraf, Chandler, AZ (US);
Henry G. Hughes, Scottsdale, AZ (US);
Craig Amrine, Tempe, AZ (US);
Ananda P. De Silva, Chandler, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
An exemplary method and apparatus for MEMS device wafer level and/or array packaging comprises inter alia an EM shielding array of dielectric lid elements () sealed to a MEMS device die array () to produce a sealed MEMS device package array (). Disclosed features and specifications may be variously controlled, adapted or otherwise optionally modified to improve hermetic sealing and/or EM shielding for any MEMS device. An exemplary embodiment of the present invention representatively provides for wafer level packaging of RF MEMS switches prior to device singulation.