The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 11, 2005
Filed:
Feb. 11, 2004
Eiichi Murakami, Tokorozawa, JP;
Akio Nishida, Tachikawa, JP;
Kazunori Umeda, Higashimurayama, JP;
Kousuke Okuyama, Kawagoe, JP;
Toshiaki Yamanaka, Iruma, JP;
Jiro Yugami, Yokohama, JP;
Shinichiro Kimura, Kunitachi, JP;
Eiichi Murakami, Tokorozawa, JP;
Akio Nishida, Tachikawa, JP;
Kazunori Umeda, Higashimurayama, JP;
Kousuke Okuyama, Kawagoe, JP;
Toshiaki Yamanaka, Iruma, JP;
Jiro Yugami, Yokohama, JP;
Shinichiro Kimura, Kunitachi, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
This semiconductor device manufacturing method comprises the steps of: forming a thick gate oxide film (thick oxide film) in a first region of a substrate, forming a thin gate oxide film (thin oxide layer) in a second region, and then, applying oxynitridation to these gate oxide films; forming gate electrodes toon these gate oxide films; and implanting an ion that contains nitrogen or nitrogen atoms into at least one part of an interface between the hick gate oxide film (thick oxide film) and the substrate before or after the step of forming the gate electrodes, thereby forming a highly oxy-nitrided region. In this manner, in a semiconductor device in which there coexist a MISFET having a thin gate insulation film and a MISFET having a thick gate insulation film, hot carrier reliability of the MISFET having the thick gate insulation film is improved.