The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 27, 2005
Filed:
Sep. 07, 2001
Peter Wohl, Williston, VT (US);
John A. Waicukauski, Tualatin, OR (US);
Thomas W. Williams, Boulder, CO (US);
Peter Wohl, Williston, VT (US);
John A. Waicukauski, Tualatin, OR (US);
Thomas W. Williams, Boulder, CO (US);
Synopsys Inc., Mountain View, CA (US);
Abstract
Deterministic ATPG test coverage is provided in a logic BIST architecture while reducing test application time and test data volume, as compared to deterministic ATPG patterns. The logic BIST architecture can include a PRPG shadow operatively coupled to a PRPG circuit. The PRPG shadow allows re-seeding of the PRPG circuit with zero cycle overhead. Two compressions can be provided. In a first compression, multiple tests for faults are compressed into one pattern. In a second compression, multiple deterministic ATPG patterns can be compressed into one seed. All patterns provided from the PRPG can be controlled by these seeds so that all care bits are properly set, while all other scan cells are set to pseudo-random values from the PRPG. In this manner, the PRPG can rapidly deliver highly pertinent data to the scan chains of the device under test.