The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 2005
Filed:
Apr. 27, 2004
Mark Vincent Pierson, Binghamton, NY (US);
Jennifer Rebecca Sweterlitsch, Vestal, NY (US);
Charles Gerard Woychik, Vestal, NY (US);
Thurston Bryce Youngs, Jr., Endicott, NY (US);
Mark Vincent Pierson, Binghamton, NY (US);
Jennifer Rebecca Sweterlitsch, Vestal, NY (US);
Charles Gerard Woychik, Vestal, NY (US);
Thurston Bryce Youngs, Jr., Endicott, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A flexible, compliant layer of a single low modulus material for connecting a chip die directly to a circuit card without encapsulation. The flexible compliant layer provides stress relief caused by CTE thermal mismatch in chip die and circuit card. An array of copper plated vias are formed in said compliant layer with each via terminating on opposing surfaces of the layer in copper pads. Rather than copper, other metals, such as gold or nickel, may also be used. An array of holes may be positioned between said array of vias to provide additional resiliency. The plated vias may be angled with respect to said opposing surfaces to allow additional vertical and horizontal stress relief. Connection of the pads on one surface to high melt C-4 solder balls or columns on a chip die results in solder filled vias. Low melt solder connection of the pads on the other surface to a circuit card allows non-destructive rework of the cards.