The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2005
Filed:
Dec. 29, 2003
Hieu Van Tran, San Jose, CA (US);
Tam Huu Tran, San Jose, CA (US);
Vishal Sarin, Santa Clara, CA (US);
Anh Ly, San Jose, CA (US);
Niang Hangzo, San Jose, CA (US);
Sang Thanh Nguyen, Union City, CA (US);
Hieu Van Tran, San Jose, CA (US);
Tam Huu Tran, San Jose, CA (US);
Vishal Sarin, Santa Clara, CA (US);
Anh Ly, San Jose, CA (US);
Niang Hangzo, San Jose, CA (US);
Sang Thanh Nguyen, Union City, CA (US);
Silicon Storage Technology, Inc., Sunnyvale, CA (US);
Abstract
A bandgap reference generator comprises a PMOS transistor and NMOS transistor in a pnp bipolar junction transistor connected in series in a first leg. The bandgap reference generator includes a second leg that includes a PMOS transistor, an NMOS transistor, a resistor and a pnp bipolar junction transistor. A bias circuit provides a bias to a mirror formed by the gates of the PMOS transistors to lower the operating voltage of the bandgap reference generator. A second biasing circuit may provide bias to the mirror formed of the NMOS transistors. A time-based and a DC bias-based start up circuitry and method is provided.