The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2005
Filed:
Jun. 12, 2002
Tatsuhiko Fujihira, Nagano, JP;
Takashi Kobayashi, Nagano, JP;
Hitoshi Abe, Nagano, JP;
Yasushi Niimura, Nagano, JP;
Masanori Inoue, Nagano, JP;
Tatsuhiko Fujihira, Nagano, JP;
Takashi Kobayashi, Nagano, JP;
Hitoshi Abe, Nagano, JP;
Yasushi Niimura, Nagano, JP;
Masanori Inoue, Nagano, JP;
Fuji Electric Holdings Co., Ltd., Tokyo, JP;
Abstract
A vertical MOS semiconductor device exhibits a high breakdown voltage and low on-resistance, reduces the tradeoff relation between the on-resistance and the breakdown voltage, and realizes high speed switching. The semiconductor device has a breakdown-voltage sustaining layer, such as an n-type drift layer, and a well region, such as a p-type well region, in the breakdown-voltage sustaining layer. The resistivity ρ (Ωcm) of the breakdown-voltage layer is within a range expressed in terms of the breakdown voltage Vbr (V). The semiconductor device also has stripe shaped surface drain regions that extend from the well region and are surrounded by the well region. The surface area ratio between surface drain regions and the well region, which includes the source region, is from 0.01 to 0.2.