The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2005
Filed:
Feb. 28, 2002
Peter Wrschka, Wappingers Falls, NY (US);
Werner Robl, Poughkeepsie, NY (US);
Thomas Goebel, Fishkill, NY (US);
Peter Wrschka, Wappingers Falls, NY (US);
Werner Robl, Poughkeepsie, NY (US);
Thomas Goebel, Fishkill, NY (US);
Infineon Technologies AG, Munich, DE;
Abstract
In a method of planarizing a semiconductor wafer, the improvement comprising polishing above metal interconnect lines to uniformly polish the topography of the wafer to a predetermined endpoint on the wafer sufficiently close above the metal interconnect lines, yet far enough away from the lines to prevent damage to the lines, comprising: a) filling gaps between metal interconnect lines of an inter metal dielectric in a wafer being formed, by depositing HDP fill on top of the metal interconnects, between the metal interconnects, and on the surface of a dielectric layer between the metal interconnects to create an HDP overfill; b) contacting the surface of HDP overfill of the processed semiconductor wafer from step a) with a fixed abrasive polishing pad; and c) relatively moving the wafer and the fixed abrasive polishing pad to affect a polishing rate sufficient to reach a predetermined endpoint and uniformly planar surface on the wafer sufficiently close above the metal interconnect lines and yet far enough away from the lines to prevent damage to the lines.