The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2005

Filed:

Jul. 25, 2003
Applicants:

Yasushi Nakashima, Hyogo, JP;

Takashi Izutsu, Hyogo, JP;

Yoshiyuki Ishigaki, Hyogo, JP;

Inventors:

Yasushi Nakashima, Hyogo, JP;

Takashi Izutsu, Hyogo, JP;

Yoshiyuki Ishigaki, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L027/108 ;
U.S. Cl.
CPC ...
Abstract

A semiconductor memory device includes a memory cell, and first and second capacitive elements. The memory cell has a pair of inverters each including first and second driver nMOS transistors and first and second TFTs, and first and second access nMQS transistors. The first and second capacitive elements is connected to the drain of first and second access nMOS transistors, the drain of first and second driver nMOS transistors, and the drain of first and second TFTs. The gate width of first and second driver nMOS transistors is set at most 1.2 times longer than the gate width of first and second access nMOS transistors.


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