The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2005

Filed:

Mar. 28, 2003
Applicants:

Jinru Bian, Newark, DE (US);

Tirthankar Ghosh, Oreland, PA (US);

Terence M. Thomas, Newark, DE (US);

Inventors:

Jinru Bian, Newark, DE (US);

Tirthankar Ghosh, Oreland, PA (US);

Terence M. Thomas, Newark, DE (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L021/302 ;
U.S. Cl.
CPC ...
Abstract

A method for planarizing metal interconnects of a semiconductor wafer includes the steps of polishing the semiconductor wafer with a polishing solution and a polishing pad to planarize the metal interconnects. The polishing solution has by weight percent, 0.15 to 5 benzotriazole, 0 to 1 abrasive, 0 to 10 polymeric particles, 0 to 5 polymer-coated particles and balance water at a pH of less than 5 and a removal rate-pressure sensitivity (d/d) of at least 750 (Å/min/psi). The polishing simultaneously accelerates removal of projecting metal from the metal interconnects with the polishing pad providing a first pressure that increases removal rate of the projecting metal; and it inhibits removal of recessed metal from the metal interconnects with the polishing pad providing a second pressure that decreases removal of the recessed metal.


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