The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 2005
Filed:
Dec. 31, 2001
Doug Larson, Santa Clara, CA (US);
Anthony Le, Santa Clara, CA (US);
Doug Larson, Santa Clara, CA (US);
Anthony Le, Santa Clara, CA (US);
Advantest Corp., Tokyo, JP;
Abstract
A time shift circuit for changing a delay timing of a portion of a test pattern for testing a semiconductor device. The time shift circuit includes a multiplexer for selectively producing delay value data indicating a value of time shift in response to a shift command signal, a vernier delay unit for producing timing vernier data based on the delay value data selected by the multiplexer, and a timing generator for generating a timing edge for the specific portion of the test pattern based on the timing vernier data from the vernier delay unit. The shift command signal sets either a normal mode where predetermined delay value data is selected by the multiplexer or a time shift mode where delay value data for shifting the timing edge in real time is selected by the multiplexer.