The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 2005
Filed:
Dec. 19, 2001
Keng L. Wong, Portland, OR (US);
Hung-piao MA, Portland, OR (US);
Tawfik M. Rahal-arabi, Tigard, OR (US);
Javed Barkatullah, Portland, OR (US);
Edward A. Burton, Hillsboro, OR (US);
Keng L. Wong, Portland, OR (US);
Hung-Piao Ma, Portland, OR (US);
Tawfik M. Rahal-Arabi, Tigard, OR (US);
Javed Barkatullah, Portland, OR (US);
Edward A. Burton, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A method and apparatus for optimizing clock distribution in a circuit to reduce the effect of power supply noise. Parameters are determined including: a response curve of a power source for a circuit, a delay sensitivity of a clock net in the circuit to the power source, a delay sensitivity of a data net in the circuit to the power source, a data delay for the data net, and a clock delay for the clock net. The clock delay is adjusted to reduce the effect of power supply noise on the data net. The adjusting is based on the response curve of the power source, the delay sensitivity of the clock net, the delay sensitivity of the data net, the data delay, and the clock delay. The adjusting includes adding a pre-distribution clock delay.