The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 2005
Filed:
Oct. 27, 2003
Bennett A. Joiner, Austin, TX (US);
Yaping Zhou, Austin, TX (US);
Ben W. Herberg, Pflugerville, TX (US);
Bennett A. Joiner, Austin, TX (US);
Yaping Zhou, Austin, TX (US);
Ben W. Herberg, Pflugerville, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A semiconductor device has a die () overlying and electrically connected to a support structure (), such as a substrate or a lead frame, via a plurality of interconnects. Aggressor interconnects () are noise sources to victim interconnects () carrying sensitive signals. An arrangement of shield interconnects () surround the victim interconnect () in a cage-like structure to significantly block noise from the aggressor interconnect. In one form the shield interconnects are ground or power supply and the victim interconnect may be, for example, a clock signal or an RF signal. The number of shield interconnects and the number of protected victim interconnects varies depending upon design requirements. Either wire bonding or other interconnect technology (e.g. bump) is applicable.