The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2005
Filed:
Jan. 30, 2004
Bernhard Kowalski, Munich, DE;
Andreas Felber, Dresden, DE;
Valentin Rosskopf, Poettmes, DE;
Juergen Lindolf, Friedberg, DE;
Till Schloesser, Dresden, DE;
Bernd Goebel, Munich, DE;
Bernhard Kowalski, Munich, DE;
Andreas Felber, Dresden, DE;
Valentin Rosskopf, Poettmes, DE;
Juergen Lindolf, Friedberg, DE;
Till Schloesser, Dresden, DE;
Bernd Goebel, Munich, DE;
Infineon Technologies AG, Munich, DE;
Abstract
An integrated circuit arrangement that has an integrated test structure is provided. The integrated circuit arrangement includes a transistor array having vertical FET selection transistors electrically coupled to storage capacitors of an assigned memory cell array, the storage capacitors being formed vertically into the depth of a substrate in deep trenches. The test structure may enable a plurality of vertical FET selection transistors by a conductive electrode material embedded in an extended deep trench. With a test structure of this type, it is possible to evaluate characteristic values for leakage currents and capacitances at different semiconductor junctions and also between different sections of the integrated circuit arrangement and also to perform reliability stress tests.