The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 09, 2005
Filed:
Mar. 27, 2003
Derryl D. J. Allman, Camas, WA (US);
James R. Hightower, Fort Collins, CO (US);
Phonesavanh Saopraseuth, Gresham, OR (US);
Derryl D. J. Allman, Camas, WA (US);
James R. Hightower, Fort Collins, CO (US);
Phonesavanh Saopraseuth, Gresham, OR (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A method for forming the electrical interconnect levels and circuit elements of an integrated circuit is provided by the present invention. The method utilizes a relatively thin layer of conductive material having a higher resistance than the metal typically used to form electrical interconnections, such as titanium nitride, to provide relatively short local interconnections between circuit elements of the integrated circuit. In addition, this same thin layer of conductive material is used to form macro elements such as capacitors, resistors, and fuses in the integrated circuit. By allowing the removal of space consuming transverse electrical interconnect lines from the interconnect levels, the present invention increases the routing density of the electrical interconnect levels. Furthermore, by allowing these local electrical interconnections to be produced during the same manufacturing step as the macro elements of the integrated circuit, the method of the present invention tends to reduce the number of steps required to produce an integrated circuit.