The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2005

Filed:

Dec. 02, 2003
Applicants:

Cyril Cabral, Jr., Ossining, NY (US);

Jakub T. Kedzierski, Peekskill, NY (US);

Victor Ku, Tarrytown, NY (US);

Christian Lavoie, Ossining, NY (US);

Vijay Narayanan, New York, NY (US);

An L. Steegen, Stanford, CT (US);

Inventors:

Cyril Cabral, Jr., Ossining, NY (US);

Jakub T. Kedzierski, Peekskill, NY (US);

Victor Ku, Tarrytown, NY (US);

Christian Lavoie, Ossining, NY (US);

Vijay Narayanan, New York, NY (US);

An L. Steegen, Stanford, CT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L021/8238 ;
U.S. Cl.
CPC ...
Abstract

A CMOS silicide metal integration scheme that allows for the incorporation of silicide contacts (S/D and gates) and metal silicide gates using a self-aligned process (salicide) as well as one or more lithography steps is provided. The integration scheme of the present invention minimizes the complexity and cost associated with fabricating a CMOS structure containing silicide contacts and silicide gate metals.


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