The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2005

Filed:

Oct. 14, 2003
Applicants:

James P. Baukus, Westlake Village, CA (US);

Lap-wai Chow, South Pasadena, CA (US);

William M. Clark, Jr., Camarillo, CA (US);

Paul Ou Yang, San Jose, CA (US);

Inventors:

James P. Baukus, Westlake Village, CA (US);

Lap-Wai Chow, South Pasadena, CA (US);

William M. Clark, Jr., Camarillo, CA (US);

Paul Ou Yang, San Jose, CA (US);

Assignees:

HRL Laboratories, LLC, Malibu, CA (US);

Promtek, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L023/04 ;
U.S. Cl.
CPC ...
Abstract

A multilayered integrated circuit and a method of designing a multilayered integrated circuit are provided. The circuit comprises at least two conductive layers and extraneous conductive lines placed in the conductive layers. The extraneous conductive lines are made of a material which is the same as the material in the conductive layers and have dimensions which are the same as the dimension of the material in the conductive layers. The extraneous conductive lines perform functions which are unnecessary to the operation of the integrated circuit and are undistinguishable from the functional conductive lines, thus burdening the work of a reverse engineer. The method of designing the multilayered circuit comprises a step of providing a computer generated representation of the extraneous conductive lines.


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