The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2005

Filed:

Mar. 10, 2003
Applicants:

Ching-hsiang Hsu, Hsin-Chu, TW;

Evans Ching-song Yang, Chan-Hua, TW;

Len-yi Leu, Hsin-Chu, TW;

Bin-shing Chen, Hsin-Chu, TW;

Inventors:

Ching-Hsiang Hsu, Hsin-Chu, TW;

Evans Ching-Song Yang, Chan-Hua, TW;

Len-Yi Leu, Hsin-Chu, TW;

Bin-Shing Chen, Hsin-Chu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L029/788 ; H01L027/108 ;
U.S. Cl.
CPC ...
Abstract

A non-volatile memory cell that includes a semiconductor substrate, a well region implanted with a first-type dopant formed in the semiconductor substrate, a first doped region implanted with a second-type dopant formed in the semiconductor substrate, a second doped region, formed spaced-apart from the first doped region, implanted with a second-type dopant formed in the semiconductor substrate, the second doped region further including a third region implanted with the first-type dopant, a first dielectric layer disposed over the semiconductor substrate, a floating gate disposed over the first dielectric layer and extending over the well region and a portion of the second doped region, a second dielectric layer disposed over the floating gate, and a control gate disposed over the first dielectric layer and the second dielectric layer.


Find Patent Forward Citations

Loading…