The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2005

Filed:

Jun. 18, 2003
Applicants:

David S. L. Mui, Fremont, CA (US);

Wei Liu, San Jose, CA (US);

Shashank C. Deshmukh, San Jose, CA (US);

Hiroki Sasano, Sunnyvale, CA (US);

Inventors:

David S. L. Mui, Fremont, CA (US);

Wei Liu, San Jose, CA (US);

Shashank C. Deshmukh, San Jose, CA (US);

Hiroki Sasano, Sunnyvale, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01B011/02 ; H01L021/66 ;
U.S. Cl.
CPC ...
Abstract

A method and apparatus for processing a semiconductor wafer is provided for reducing CD microloading variation. OCD metrology is used to inspect a wafer to determine pre-etch CD microloading, by measuring the CD of dense and isolated photoresist lines. Other parameters can also be measured or otherwise determined, such as sidewall profile, photoresist layer thickness, underlying layer thickness, photoresist pattern density, open area, etc. The inspection results are fed forward to the etcher to determine process parameters, such as resist trim time and/or etch conditions, thereby achieving the desired post-etch CD microloading. In certain embodiments, the CD and profile measurements, trim, etch processing and post-etch cleaning are performed at a single module in a controlled environment. All of the transfer and processing steps performed by the module are performed in a clean environment, thereby increasing yield by avoiding exposing the wafer to the atmosphere and possible contamination between steps.


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