The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 26, 2005
Filed:
Apr. 18, 2003
Circuit device with at least partial packaging, exposed active surface and a voltage reference plane
George R. Leal, Cedar Park, TX (US);
Jie-hua Zhao, Austin, TX (US);
Edward R. Prack, Austin, TX (US);
Robert J. Wenzel, Austin, TX (US);
Brian D. Sawyer, Mesa, AZ (US);
David G. Wontor, Austin, TX (US);
Marc Alan Mangrum, Manchaca, TX (US);
George R. Leal, Cedar Park, TX (US);
Jie-Hua Zhao, Austin, TX (US);
Edward R. Prack, Austin, TX (US);
Robert J. Wenzel, Austin, TX (US);
Brian D. Sawyer, Mesa, AZ (US);
David G. Wontor, Austin, TX (US);
Marc Alan Mangrum, Manchaca, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A circuit device () is placed within an opening of a conductive layer () which is then partially encapsulated with an encapsulant () so that the active surface of the circuit device () is coplanar with the conductive layer (). At least a portion of the conductive layer () may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device () may be placed on a conductive layer () such that an active surface of circuit device () is between conductive layer () and an opposite surface of circuit device (). The conductive layer () has at least one opening () to expose the active surface of circuit device (). The encapsulant () may be electrically conductive or electrically non-conductive.