The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 26, 2005
Filed:
Oct. 14, 2003
Hsiu Ouyang, Taipei, TW;
Chi-hsin Lo, Chu-Pei, TW;
Chen-ming Huang, Jungli, TW;
Chia-ta Hsieh, Tainan, TW;
Chia-shiung Tsai, Hsin-Chu, TW;
Hsiu Ouyang, Taipei, TW;
Chi-Hsin Lo, Chu-Pei, TW;
Chen-Ming Huang, Jungli, TW;
Chia-Ta Hsieh, Tainan, TW;
Chia-Shiung Tsai, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin Chu, TW;
Abstract
A split gate FET wordline electrode structure and method for forming the same including an improved polysilicon etching process including providing a semiconductor wafer process surface comprising first exposed polysilicon portions and adjacent oxide portions; forming a first oxide layer on the exposed polysilicon portions; blanket depositing a polysilicon layer on the first exposed polysilicon portions and adjacent oxide portions; forming a hardmask layer on the polysilicon layer; carrying out a multi-step reactive ion etching (RIE) process to etch through the hardmask layer and etch through a thickness portion of the polysilicon layer to form second polysilicon portions adjacent the oxide portions having upward protruding outer polysilicon fence portions; contacting the semiconductor wafer process surface with an aqueous HF solution; and, carrying out a downstream plasma etching process to remove polysilicon fence portions.