The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 19, 2005
Filed:
Jul. 21, 1999
Kaori Umezawa, Kanagawaken, JP;
Norihiko Tsuchiya, Tokyo, JP;
Yoshiaki Matsushita, Kanagawaken, JP;
Hiroyuki Kamijou, Kanagawaken, JP;
Atsushi Yagishita, Kanagawaken, JP;
Tsunehiro Kita, Kanagawaken, JP;
Kaori Umezawa, Kanagawaken, JP;
Norihiko Tsuchiya, Tokyo, JP;
Yoshiaki Matsushita, Kanagawaken, JP;
Hiroyuki Kamijou, Kanagawaken, JP;
Atsushi Yagishita, Kanagawaken, JP;
Tsunehiro Kita, Kanagawaken, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A semiconductor substrate having a shallow trench isolation (STI) structure and a method of manufacturing the same are provided, i.e., an isolation substrate in which grooves are selectively formed at predetermined locations of the semiconductor substrate and oxide films using organic silicon source as material are buried in the grooves as buried oxide films. The present invention is characterized in that the buried oxide films are annealed at a predetermined temperature within the range of 1100 to 1350° C. before or after planarization of the semiconductor substrate such that ring structures of more than 5-fold ring and ring structures of less than 4-fold ring are formed at predetermined rates in the buried oxide films. The above annealing allows stress of the oxide film buried in the grooves to be relaxed. Hence, the generation of dislocation is suppressed.