The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2005

Filed:

Jan. 24, 2002
Applicants:

Satoshi Kumaki, Hyogo, JP;

Tetsuya Matsumura, Hyogo, JP;

Hiroshi Segawa, Hyogo, JP;

Atsuo Hanami, Hyogo, JP;

Vasile Mosneaga, Fukuoka-shi, Fukuoka 814-0144, JP;

Inventors:

Satoshi Kumaki, Hyogo, JP;

Tetsuya Matsumura, Hyogo, JP;

Hiroshi Segawa, Hyogo, JP;

Atsuo Hanami, Hyogo, JP;

Vasile Mosneaga, Fukuoka-shi, Fukuoka 814-0144, JP;

Assignees:

Renesas Technology Corp., Tokyo, JP;

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F012/00 ;
U.S. Cl.
CPC ...
Abstract

When the CPU writes data into a memory, a 0 detection circuit detects the number of bits having the value 0 from the data. When the number of bits with 0 is equal to or larger than the number of bits with 1, the data output from the CPU is provided to the memory under control of a selector. When the number of bits with 0 is fewer than the number of bits with 1, the data output from the CPU is inverted and provided to the memory under control of the selector. Accordingly, the rewriting frequency of each memory cell from 0 to 1 or from 1 to 0 in the memory can be reduced in average. Thus the power consumption of the memory in a data writing mode can be reduced.


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