The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2005

Filed:

Aug. 02, 2002
Applicants:

Atsushi Kanda, Suwa, JP;

Yasushi Haga, Sakata, JP;

Inventors:

Atsushi Kanda, Suwa, JP;

Yasushi Haga, Sakata, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L021/8234 ;
U.S. Cl.
CPC ...
Abstract

A procedure of manufacturing a semiconductor device according to the present invention first creates a gate electrode on a center portion of a gate oxide film formed on a substrate, forms a silicon oxide film over the whole surface of the substrate including the gate electrode, and etches the whole face of the silicon oxide film, so as to form a side wall of the silicon oxide film on a side face of the gate electrode. The procedure then implants an impurity ion according to a channel of a target MOS transistor, so as to specify a drain area and a source area. In the process of specifying the drain area and the source area, a resist is formed in advance on at least a peripheral portion of the gate oxide film in a high-breakdown-voltage MOS transistor, so as to prevent implantation of the impurity ion in an under-layer region below the peripheral portion of the gate oxide film. This arrangement enables both a high-breakdown-voltage MOS transistor and a low-breakdown-voltage MOS transistor to be efficiently formed on an identical substrate without damaging the characteristics of the respective transistors.


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