The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 05, 2005
Filed:
Nov. 20, 2001
Kun-lin Wu, Taichung, TW;
Meng-jin Tsai, Kaohsiung, TW;
Kun-Lin Wu, Taichung, TW;
Meng-Jin Tsai, Kaohsiung, TW;
United Microelectronics Corp., Hsinchu, TW;
Abstract
A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 Å can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiHCl) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second metallic line that couples electrically with the first metallic line through the via opening is formed.