The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 21, 2005
Filed:
Jul. 16, 2001
Shigeki Tanaka, Hakodate, JP;
Atsushi Fujisawa, Hakodate, JP;
Souichi Nagano, Hokkaido, JP;
Tsugihiko Hirano, Hakodate, JP;
Ryouichi Oota, Hokkaido, JP;
Takafumi Konno, Hakodate, JP;
Kenichi Tatebe, Hakodate, JP;
Toshiaki Okamoto, Hakodate, JP;
Shigeki Tanaka, Hakodate, JP;
Atsushi Fujisawa, Hakodate, JP;
Souichi Nagano, Hokkaido, JP;
Tsugihiko Hirano, Hakodate, JP;
Ryouichi Oota, Hokkaido, JP;
Takafumi Konno, Hakodate, JP;
Kenichi Tatebe, Hakodate, JP;
Toshiaki Okamoto, Hakodate, JP;
Renesas Technology Corp., Tokyo, JP;
Hitachi Hokkai Semiconductor, Ltd., Hokkaido, JP;
Abstract
A semiconductor device includes a substrate, a semiconductor chip mounted on one surface of the substrate, wherein the semiconductor chip has an integrated circuit and bonding pads formed on a main surface thereof. The main surface of the semiconductor chip has a quadrilateral shape with the bonding pads being disposed along four sides of the main surface. A plurality of conductors is disposed on the one surface of the substrate so as to surround the semiconductor chip along four sides thereof and a plurality of bonding wires electrically connect the bonding pads with tips of the conductors, respectively. A resin body seals the semiconductor chip, the conductors and the plurality of bonding wires. A pitch between adjacent bonding pads increases in a direction toward four corners defined by the four sides of the main surface of the semiconductor chip.