The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 21, 2005
Filed:
Sep. 20, 2002
Lloyd G. Burrell, Poughkeepsie, NY (US);
Douglas Kemerer, Essex Junction, VT (US);
Henry A. Nye, Iii, Brookfield, CT (US);
Hans-joachim Barth, Munich, DE;
Emmanuel F. Crabbe, Chappaqua, NY (US);
David Anderson, Gulf Shores, AL (US);
Joseph Chan, Fishkill, NY (US);
Lloyd G. Burrell, Poughkeepsie, NY (US);
Douglas Kemerer, Essex Junction, VT (US);
Henry A. Nye, III, Brookfield, CT (US);
Hans-Joachim Barth, Munich, DE;
Emmanuel F. Crabbe, Chappaqua, NY (US);
David Anderson, Gulf Shores, AL (US);
Joseph Chan, Fishkill, NY (US);
Infineon Technologies AG, Munich, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A semiconductor device () having support structures () beneath wirebond regions () of contact pads () and a method of forming same. Low modulus dielectric layers () are disposed over a workpiece (). Support structures () are formed in the low modulus dielectric layers (), and support vias () are formed between the support structures (). A high modulus dielectric film () is disposed between each low modulus dielectric layer (), and a high modulus dielectric layer () is disposed over the top low modulus dielectric layer (). Contact pads () are formed in the high modulus dielectric layer (). Each support via () within the low modulus dielectric layer () resides directly above a support via () in the underlying low modulus dielectric layer (), to form a plurality of via support stacks within the low modulus dielectric layers ().