The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2005

Filed:

Feb. 11, 2004
Applicants:

Chyiu-hyia Poon, Singapore, SG;

Byung Jin Cho, Singapore, SG;

Yong Feng LU, Lincoln, NE (US);

Alex See, Singapore, SG;

Mousumi Bhat, Singapore, SG;

Inventors:

Chyiu-Hyia Poon, Singapore, SG;

Byung Jin Cho, Singapore, SG;

Yong Feng Lu, Lincoln, NE (US);

Alex See, Singapore, SG;

Mousumi Bhat, Singapore, SG;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L021/336 ; H01L021/20 ; H01L021/36 ; H01L021/265 ;
U.S. Cl.
CPC ...
Abstract

A method for forming a highly activated ultra shallow ion implanted semiconductive elements for use in sub-tenth micron MOSFET technology is described. A key feature of the method is the ability to activate the implanted impurity to a highly active state without permitting the dopant to diffuse further to deepen the junction. A selected single crystalline silicon active region is first amorphized by implanting a heavy ion such as silicon or germanium. A semiconductive impurity for example boron is then implanted and activated by pulsed laser annealing whereby the pulse fluence, frequency, and duration are chosen to maintain the amorphized region just below it's melting temperature. It is found that just below the melting temperature there is sufficient local ion mobility to secure the dopant into active positions within the silicon matrix to achieve a high degree of activation with essentially no change in concentration profile. The selection of the proper laser annealing parameters is optimized by observation of the reduction of sheet resistance and concentration profile as measured on a test site. Application of the method is applied to forming a MOS FET and a CMOS device. The additional processing steps required by the invention are applied simultaneously to both n-channel and p-channel devices of the CMOS device pair.


Find Patent Forward Citations

Poon, Chyiu-Hyia. (2005). Method of multiple pulse laser annealing to activate ultra-shallow junctions (U.S. Patent No. 6897118). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6897118

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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