The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6897111 B1

PDF
Full Text
Expired
Date of Patent:
May. 24, 2005

Filed:

Jul. 28, 2003
Applicants:

Elgin Quek, Singapore, SG;

Jia Zhen Zheng, Singapore, SG;

Pradeep R. Yelehanka, Singapore, SG;

Weining LI, Shanghai, CN;

Inventors:

Elgin Quek, Singapore, SG;

Jia Zhen Zheng, Singapore, SG;

Pradeep R. Yelehanka, Singapore, SG;

Weining Li, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L021/336 ;
U.S. Cl.
CPC ...
Abstract

A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a horizontal semiconductor fin on top of the semiconductor substrate. An access transistor gate and a thyristor gate are then formed on top of the semiconductor substrate and in contact with the horizontal semiconductor fin. An access transistor is formed from at least a portion of the horizontal semiconductor fin and the access transistor gate. A thyristor is formed from at least a portion of the horizontal semiconductor fin and the thyristor gate, the access transistor being in contact with the thyristor.


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Quek, Elgin. (2005). Method using quasi-planar double gated fin field effect transistor process for the fabrication of a thyristor-based static read/write random-access memory (U.S. Patent No. 6897111). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6897111

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