The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 24, 2005
Filed:
Nov. 26, 2002
Yi He, Sunnyvale, CA (US);
Wei Zheng, Santa Clara, CA (US);
Zhizheng Liu, Sunnyvale, CA (US);
Mark W. Randolph, San Jose, CA (US);
Darlene G. Hamilton, San Jose, CA (US);
Ken Tanpairoj, Palo Alto, CA (US);
Yi He, Sunnyvale, CA (US);
Wei Zheng, Santa Clara, CA (US);
Zhizheng Liu, Sunnyvale, CA (US);
Mark W. Randolph, San Jose, CA (US);
Darlene G. Hamilton, San Jose, CA (US);
Ken Tanpairoj, Palo Alto, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A method of fabricating a memory array, while protecting it from charge damage. Bitlines that may have source/drain regions of memory cells are formed in a substrate. Wordlines are formed above the bitlines and may have gate regions. Next, a first metal region that is coupled to one of the bitlines is formed above the bitlines. A second metal region that is not electrically coupled to the first metal region is formed. Then, the first metal region is electrically coupled to the second metal region. Charge damage is reduced by keeping the antenna ratio between the first metal region and the bitline low. For further protection, a diode or fuse may also be formed between the substrate and the portion of the metal region that is coupled to the bitline. Also, fuse may be formed between a bitline and a wordline to protect the wordline.