The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 10, 2005
Filed:
Sep. 28, 2004
Heemyong Park, La Grangeville, NY (US);
Byoung H. Lee, Wappingers Falls, NY (US);
Paul D. Agnello, Wappingers Falls, NY (US);
Dominic J. Schepis, Wappingers Falls, NY (US);
Ghavam G. Shahidi, Pound Ridge, NY (US);
Heemyong Park, La Grangeville, NY (US);
Byoung H. Lee, Wappingers Falls, NY (US);
Paul D. Agnello, Wappingers Falls, NY (US);
Dominic J. Schepis, Wappingers Falls, NY (US);
Ghavam G. Shahidi, Pound Ridge, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer, forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and hearing the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.