The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 26, 2005
Filed:
Nov. 27, 2002
Mark A. Durlam, Chandler, AZ (US);
Jeffrey H. Baker, Chandler, AZ (US);
Brian R. Butcher, Gilbert, AZ (US);
Mark F. Deherrera, Tempe, AZ (US);
John J. D'urso, Chandler, AZ (US);
Earl D. Fuchs, Phoenix, AZ (US);
Gregory W. Grynkewich, Gilbert, AZ (US);
Kelly W. Kyler, Mesa, AZ (US);
Jaynal A. Molla, Gilbert, AZ (US);
J. Jack Ren, Phoenix, AZ (US);
Nicholas D. Rizzo, Gilbert, AZ (US);
Mark A. Durlam, Chandler, AZ (US);
Jeffrey H. Baker, Chandler, AZ (US);
Brian R. Butcher, Gilbert, AZ (US);
Mark F. Deherrera, Tempe, AZ (US);
John J. D'Urso, Chandler, AZ (US);
Earl D. Fuchs, Phoenix, AZ (US);
Gregory W. Grynkewich, Gilbert, AZ (US);
Kelly W. Kyler, Mesa, AZ (US);
Jaynal A. Molla, Gilbert, AZ (US);
J. Jack Ren, Phoenix, AZ (US);
Nicholas D. Rizzo, Gilbert, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method for fabricating a cladded conductor () for use in a magnetoelectronics device is provided. The method includes providing a substrate () and forming a conductive barrier layer () overlying the substrate (). A dielectric layer () is formed overlying the conductive barrier layer () and a conducting line () is formed within a portion of the dielectric layer (). The dielectric layer () is removed and a flux concentrator () is formed overlying the conducting line ().